High processing speed in currently available data processors must be supported by large amounts of high speed random access memory. Due to reduced device counts per memory cell, much of the required storage is provided by dynamic random access memories (DRAMs) so that a significantly greater number of memory cells can be provided on a single integrated circuit chip. In such devices, the density at which memory cells, principally comprising one storage capacitor per memory cell, is of great importance since the capacitance of each capacitor is very limited due to small size, while that capacitance must be large compared to the capacitance of the word line and bit line to achieve adequate operating margins for the sense amplifiers used to detect the presence or absence of stored charge. Therefore, the trenches are formed to relatively large depths while being very closely spaced. These same geometries are also important for other trench structures such as isolation trenches.
In recent years, it has also been the practice to provide a buried plate within the semiconductor substrate in which the trench capacitors are formed. The buried plate is a region surrounding the sides and bottom of a storage node trench in the dynamic random access memory cell which acts as the fixed potential terminal for the storage capacitor. The buried plate typically goes down the sides of the storage node trench about 6 microns. The depth at which the top surface of the buried plate is located should be a set distance such as 1.5.+-.0.15 microns below the surface of the semiconductor substrate. This depth of the buried plate is typically referred to as D.sub.BP.
The buried plate can be fabricated using resist recess processing along with outdiffusing of a dopant such as arsenic from the lower portion of a trench. U.S. Pat. No. 5,618,751 to Golden et al and assigned to International Business Machines Corporation describes one such process. The resist recess depth and the buried plate depth are critical parameters for the trench capacitor.
Currently, measuring the buried plate depth as well as that for other buried interface structures can only be carried out destructively by cross-section and microscopic imaging of random samples. Accordingly, providing a practical and non-destructive procedure for determining the depth at which the top surface of a buried interface is located would represent a significant advance.